Classifier Instance:

Anchor text: arbitrate
Target Entity: Arbiter_\u0028electronics\u0029
Preceding Context: A PCI architecture has no central DMA controller, unlike ISA. Instead, any PCI component can request control of the bus ("become the bus master") and request to read from and write to system memory. More precisely, a PCI component requests bus ownership from the PCI bus controller (usually the southbridge in a modern PC design), which will
Succeeding Context: if several devices request bus ownership simultaneously, since there can only be one bus master at one time. When the component is granted ownership, it will issue normal read and write commands on the PCI bus, which will be claimed by the bus controller and forwarded to the memory controller using a scheme which is specific to every chipset.
Paragraph Title: PCI
Source Page: Direct memory access

Ground Truth Types:

|---wordnet_entity_100001740
|  |---wordnet_artifact_100021939
|  |  |---wordnet_instrumentality_103575240
|  |  |  |---wordnet_device_103183080
|  |  |  |  |---wordnet_device_103183080_rest

Predicted Types:

TypeConfidenceDecision
wordnet_artifact_100021939-1.069732990251714 0
wordnet_event_100029378-0.808439502333448 0
wordnet_organization_108008335-1.1222792861373583 0
wordnet_person_100007846-0.8171846541766251 0
yagoGeoEntity-1.612242495996132 0
|---wordnet_entity_100001740
|  |---wordnet_artifact_100021939
|  |---wordnet_event_100029378
|  |---wordnet_organization_108008335
|  |---wordnet_person_100007846
|  |---yagoGeoEntity